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Koh Young to share insights on advanced package inspection solutions

SMTA Wafer-Level Packaging Symposium
Koh Young to share insights on advanced package inspection solutions

Koh Young to share insights on advanced package inspection solutions
The SMTA WLPS will explore the massive changes in advanced package technology because electrical system architects are directly driving package performance requirements, something which has never happened before. Source: Koh Young

Koh Young Technology will present on its Multimodal Phase Shift Optics Approach to high-speed 3D reconstruction of semiconductor and advanced packages at the SMTA Wafer-Level Packaging Symposium in Burlingame, CA on 13 February 2024.During the event, Dr. Seung Hyun Lee, Ph.D. will present the paper “High-Speed Die and Component 3D Reconstruction Solution by Multimodal Phase Shift Optics Approach”. Therein he will explain how advancements in optical 3D measurement and the integration of Artificial Intelligence (AI) have paved the way for advanced packaging applications. Multi-modal measurement probes, equipped with enhanced depth of focus, can cover height differences in the latest package designs. Various surface conditions of components, chips, and surfaces are measured by combining an oblique optical system, which ensures stable high-speed measurement of objects with diffuse reflection, with a coaxial optical system, suitable for measuring objects with specular reflection. The integration of AI deep learning technology enables effective processing of various noises encountered during the measurements.The SMTA WLPS will explore the massive changes in advanced package technology because electrical system architects are directly driving package performance requirements, something which has never happened before. Previously System Architects designed circuits around package limitations because pushing package technologies outside of their “comfort zones” often led to undesirable results. With the rise in transistor costs and the need to improve power efficiency, Silicon Architects have little choice but to push advanced package technologies well beyond their comfort zones. The Symposium will bring together the semiconductor industry’s most respected authorities to address all aspects of wafer-level, 3D device packaging, advanced manufacturing & test technologies. Addressing wafer-level packaging, 3D, and Advanced Manufacturing & Test technologies, the conference will feature attendees from around the globe in the heart of Silicon Valley to immerse themselves in the latest technology and business trends.

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