Goepel electronic, a worldwide leading vendor of JTAG/Boundary Scan solutions compliant with IEEE Std 1149.x, introduces a new series of intelligent tools, particularly developed for the simulation based test of circuit functionalities, within the software platform System Cascon from version 4.4.2 onwards. The tools are based on IEEE Std 1445 Digital Test Interchange Format (DTIF), and according to the company enable a hitherto unrivalled flexibility in utilising functional tests for boards and systems with integrated Boundary Scan architecture. In particular, the seamless coupling to the CAE environment of Teradyne’s Lasar simulator is the focal point of practical utilisation. “This new solutions allows to achieve a totally new quality in the combination of structural Boundary Scan test and functional cluster test based on a consistent platform”, Thomas Wenzel, managing director of Goepel electronic’s Boundary Scan Division, announces. “Especially on the field of non Boundary Scan circuitries, our customers will benefit from the significantly improved verification, test and diagnostic quality, which leads to shorter repair times will be shortened and reduced costs.” At the heart of the new solution, there is an Automated Test Program Generator (ATPG) with a specific software processor for pin fault diagnostic (PFD). The existing functional test sequences in IEEE Std. 1455 format are automatically transferred by the ATPG to respective Boundary Scan pins or virtual I/O channels, and a test program is generated as Caslan/Cascon language) source code. Parallel, the import of the entire associated fault dictionary into the project data base is executed. Channels, declared virtual, can be mapped to nearly every I/O hardware by the Hyscan technology at test time. The test program, generated by the ATPG, might stepwise be processed via the integrated multi mode debugger, altered and executed. For all 1149.x components as well as all virtual I/O channels, there is the opportunity to visualise all registers, TAP states and logic levels on nets and pins which is highly supportive in fault analysis. The compiled test programs are cross-compatible to all Goepels electronic Boundary Scan controllers. Following the test execution an automatic fault diagnostic on pin level is executed by the PFD. Detected faults can immediately be visualised in the layout per integrated ScanVision.
electronica, booth A1.542
EPP Europe 438
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