More and more complex applications are expected to be supported by mobile devices in future. Sophisticated features as needed by high-definition cameras, built-in music players, tv, video communications, navigation and mobile telephony, will drive the need for faster memory chips with more capacity and functionality. To accommodate the memories and maintain a compact footprint, devices like NAND flash, NOR flash or SDRAM will be assembled according to system needs in Multi Chip Packages (MCP). Advantest’s T 5781 is a flexible test system that solves the challenges of MCP assembly test for high volumes while offering low test costs.
Time to market: In the past, component lifetimes for consumer products were longer than now. Today’s consumers regularly replace mobile equipment, on average every second year, end users replace mobile phones with a newer more sophisticated model. This consumer driven market poses challenges to manufactures to continually launch new products on time and ahead of the competition, thus time to market is essential. Chip test and device qualification are critical processes that impact time to market. The T 5781 high parallel MCP tester contributes to achieving fast time to market while offering low test costs by supporting high parallel testing. Addressing the need to develop test program in advance of device availability, a possibility for conducting offline simulation is needed. The company offers a simulator product called TESIM for test program preparation and debug without the need to use tester hardware. For test program and device engineering verification, a small version of the test system that can be located in a office environment is available. T 5781 ES, fully compatible to the production system, offers flexibility and thus reduces costs. It can be docked to a handler for small volume production testing.A high degree of test program compatibility among the family of memory test systems keeps coding efforts low. The system can be programmed in a C++ language or the established ATL test language, allowing manufacturers to port a large base of existing test programs with minimum effort. The test system software contains an extensive library of software tools for easy device characterization and test program debugging. Such tools include; Fail Bit Mapping tool to view cells that failed a functional test, Wave Tracer tool to verify signals and patterns applied to the chip, Shmoo tool for evaluation, Pin Monitor tool to get an overview of the actual tester settings, Wafer Mapping tools to evaluate the yield on the Wafer, to name but a few. All these graphical tools are bundled to the Linux based FutureSuite system software.
Flexibility
The digital pins of a memory chip can be classified in IO pins and receiver pins. The receiver pins are connected to the chip control circuits, whereas IO pins serve as the interface for bi-directional data transfer. As more or less all memory devices have a similar structure, memory test systems usually provide a defined number of drivers and IOs per device. In general, the amount of drivers and IOs can vary for different device types. For example, some DRAMs have 16 IOs for data transfer, whereas a NAND flash typically has 8 IOs for data transfer. Due to this fact tester resources may not be used optimally for every application. T 5781 is equipped only with IOs to address a wide spectrum of device types. This affords much more flexibility to assign the tester resources for different device types.
For flash memory testing a per-site architecture test system is judged to be most effective to optimize test times. One reason is that the programming duration of a NAND flash differs from chip to chip. On T 5781 one site consists of an adequate amount of IOs and can be considered as an independent tester. The system is equipped with up to 128 test sites and the T 5781 ES with up to 8 test sites. Flexibility to test devices with large pin counts is needed and several sites can be linked together for testing large pin count devices.
Market demands MCPs to get faster, T 5781 by offering operating speed of 266 MHz (DDR 533 Mbps) covers anticipated frequency developments. The system can be docked to a wafer prober offering a solution for Know Good Die (KGD) testing. Manufacturing technology in future will enable the assembly of more and more complex MCPs containing multiple dies, additionally end applications continue to drive needs for more different MCP types. Testing the different chips inside a MCP with different testers or with different High Fidelity Fixtures (HiFix) is possible, but probably an expensive solution. T5781 offers a matrix solution enabling the tester resource to be reallocated during the test flow. This allows the connection between the tester IOs channels and MCP pins to be changed without the need to change HiFix
Dedicated testing features
Different types of memory devices often need dedicated tester features and T 5781 offers a wide variety of features, examples of which are: Bad Block Managements (BBM), Address Fail Memory (AFM), Universal Buffer Memory (UBM), Error Correction Code (ECC) mechanism, per site Algorithmic Pattern Generator (ALPG) to refresh DRAM devices during testing thus avoiding data loss and confirming data is retained within specification.
To compensate the physical design and topologies, data and address scramblers are available to allow patterns to be programmed logically. BBM is a must for NAND testing, this additional HW allows physical blocks of memory that have failed functional tests to be masked in real time from further testing thus saving time. The tester ECC function simulates the error correction performed usually in the application by the controller. As a result errors that will be corrected by the application are tolerated during test thus increasing the final yield.
Defective cells identified during a functional test can be captured into a dedicated memory (AFM) that mirrors the actual device status. This memory can be used as a basis for repair analysis or to analyze failure causes. The tester is equipped with a full logic vector generator and algorithmic pattern generator (ALPG) for DFT and logic device testing. For writing individual data to devices during test, the system is equipped with a per pin vector memory (UBM) that can be loaded during pattern run for applying trimming and repair data.
Conclusion
The memory test system T 5781 offers a comprehensive test solution for MCP, covering future testing requirements generated by increased demand for more complex MCP assemblies. It offers performance, high throughput, and flexibility to test various kinds of MCPs. The system reduces test costs and makes shorter time to market feasible.
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Zusammenfassung
Das im Beitrag vorgestellte Memory Test System bietet eine umfassende Testlösung im Bereich der Großserienproduktion (High Volume) für Multi Chip Packages (MCP). Das System deckt auch zukünftige Anforderungen ans Testen ab, die durch die erhöhte Nachfrage nach immer komplexeren MCP Baugruppen entstehen. Es verringert die Testkosten und ermöglicht eine schnellere Produkteinführungszeit.
Le Memory Test System présenté dans l’article offre une solution de test globale dans le domaine de la production en grande série (High Volume) pour les modules multipuce (Multi Chip Packages- MCP). Le système couvre également les exigences futures en termes de tests, qui découlent de la demande élevée concernant des composants MCP de plus en plus complexes. Ce système permet de réduire les frais de test et d’accélérer le délai de commercialisation du produit.
Il Memory Test System presentato nel contributo offre una completa soluzione di test nell’ambito della grande produzione di serie (High Volume) per Multi Chip Packages (MCP). Il sistema copre anche esigenze future per quando riguarda i test, esigenze che nascono dall’elevata richiesta di componenti MCP sempre più complessi. Riduce i costi dei test e rende possibile un tempo di lancio del prodotto più rapido.
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