Boundary-Scan in the limelight

The ProVision environment can also be used to check designs with regard to the Boundary-Scan test coverage. Accurate quantitative results for testability – both for the theoretical and the actually achieved test coverage – can be represented for each network and pin. The theoretical or maximum achievable test coverage can be used prior to production to ascertain whether the DFT targets of the designs have been reached or not. Based on the actual test coverage, the test developer can then determine whether the potential test coverage of the Boundary-Scan implementation has been realised.

This new version of ProVision features a direct link with JTAG Visualizer, enabling pins or networks to be displayed in real time in circuit diagrams and layouts. Areas of interest are highlighted in colour, giving the developer a rapid overview of the testability analysis results. On-screen presentation of circuit diagrams and layouts allows DFT targets to be achieved considerably more quickly than is the case with the paper copies that are usually used.

ProVision’s device library has been expanded and now includes models for over 10,000 non-boundary-scan-parts. Furthermore, user-generated IBIS and ABEL models can be handled directly by the tool, and the built-in editor allows a user to easily create additional models. As the user library expands, it is always available for re-use on subsequent projects, minimizing the application development cycle.

Other new features of the latest software tool include test generation of clusters of non-scan devices spanning multiple boards and the ability to single-step test execution for debugging and verification. As with previous releases, JTAG ProVision remains fully compatible with the prior “Classic” development tools as well as with all of our production systems. The latest release is available free of charge to customers with valid contracts.

Boundary-Scan testing is in principle a structural test method verifying whether the right devices are mounted on the board and whether all interconnects between devices are present on the board as planned, that is, non missing, and none not planned for (shorts). Structural testing has the advantage that fast, accurate diagnostics of failures is possible down to the component pin level and that the actual fault coverage of a test can be calculated, something which is impossible for functional test methods. Boundary-Scan testing requires no fixturing, is independent of the functionality of the board and can be used with any board dimension and any chip type package. Dense PCB assemblies and boards that use for example BGA packages generally lack physical access to the pins and therefore can not be tested with traditional structural test methods such as In-Circuit test. However, when Boundary-Scan is used no physical access is required and also dense PCB assemblies and boards using BGA, or other advanced surface mount packages can therefore easily be tested with Boundary-Scan.

IEEE 1149.1 (also referred to as “Dot1”) is specifically meant for digital interconnect testing. Since its official release in 1990 extensions to the Dot1 standard have been released such as IEEE 1149.4 (Dot4) for analog testing and IEEE 1149.6 (Dot6) for high speed and AC-coupled interconnects.

In-system programming has a number of advantages. First of all only un-programmed parts need to be held in stock, thus avoiding extra logistical handling in a factory to deal with special type numbers for identical parts that have been programmed differently. When in-system programming is used programmable devices only have to be handled once during board assembly thus avoiding the problem of bad contacting and the risk of damaging the device leads during programming, which can occur when traditional off-line programming is used.

Another big advantage of in-system programming is the fact that systems can be re-programmed in the field for upgrading purposes. The in-system re-programming is furthermore very beneficial during the design process. Rather then removing a part, program it and then re-install it to the board a design engineer can now quickly re-program a device during design debugging as often as needed while it is sitting on the board and thus without any additional handling of that device.

As a first rule the Boundary-Scan chains of the devices that are present in a design need to be daisy-chained into one or more big chains. Another important design rule is: provide access from a Boundary-Scan device to the enable / disable pins of non-boundary-scan devices. This makes it possible to control those pins to avoid driver conflicts that might otherwise result during Boundary-Scan testing. Also it allows for improving the fault-coverage on a board. When flashes are programmed speed is important. The programming speed can be optimized, and thus the programming time be kept minimal, by making the Boundary-Scan chain used for programming the flash as short as possible, this can be done by putting certain devices in the chain in “bypass”, or by using different Boundary-Scan chains in a board design. Also direct access to the write control pin of a flash (“autowrite”) helps to reduce the programming time by a factor of 2 to 3.

A Boundary-Scan chain is a serial path through which data is shifted using the IEEE 1149.1 protocol. Special equipment, so called Boundary-Scan controllers, is needed to shift the data through the Boundary-Scan chains at high speed during testing and in-system programming. The Boundary-Scan controller must comply with the Dot1 protocol in order to communicate with the chains.

Important aspects are speed (TCK rate), here it is important to note that the TCK frequency of the board (or the Boundary-Scan devices on the board) determine the actual rate at which data can be shifted through the Boundary-Scan chain. A Boundary-Scan controller that can handle a sustained TCK rate of 40 MHZ is generally more than enough. Next it is important to determine whether only Boundary-Scan testing, or also in-system programming is needed. In-system programming puts other requirements on the controller. Having a Boundary-Scan controller that is equipped with dedicated hardware for high performance in-system programming is essential for realizing a high throughput.

From a software perspective you want to be able to choose from different integration possibilities in addition to having a stand-alone solution. Hence selecting a Boundary-Scan controller with its associated software that can be integrated into any production environment is essential. The Boundary-Scan controller could be integrated with an in-circuit tester or a flying-probe tester. The Boundary-Scan system can also be integrated in a functional test station that runs under a customer defined user interface or under any of the software platforms provided by National Instruments for example.

As said in the beginning Boundary-Scan is an excellent tool for performing structural tests on PCBs, even for testing complete systems. If traditionally only functional testing is used, then Boundary-Scan can simply be added to the functional test environment as “pre-screening” to easily detect and diagnose soldering defects, defects which are far more difficult to detect and diagnose using functional testing.

Boundary-Scan can also be used in combination with In-Circuit testing. With the increasing density of PCBs and the use of surface mount packages the fault coverage that can be obtained with in-circuit testers has decreased dramatically. Adding Boundary-Scan can again increase the overall fault coverage. In that case Boundary-Scan can be used to test the digital part of the PCB while the In-Circuit tester could test the analog part (if Dot4 is not used for that). Rather than using an expensive In-Circuit tester for testing the analog part a much lower cost manufacturing defects analyzer (MDA) could also be used for testing the analog part. Using the integration possibilities as explained earlier Boundary-Scan can also be easily integrated with such systems.

EPP Europe 406