Research groups and IC manufacturers are scrambling for a part of the 3D action. And the first appliances with 3D chips are already available, with many more to come. But there are also a lot of questions surrounding 3D. Will 3D be limited to niche applications or will it become a widespread technology, as common as 2D CMOS process technology today? What is the roadmap for 3D, and which of the many technical options will be used? Will 3D allow us to maintain the Moore momentum? Will 3D be cost-effective? Commercial 3D chips are mainly packages of Flash memory chips used, for example, in USB sticks or solid-state disks. Essentially, what we do is take a number of 2D chips and wirebond them in one package. This is a packaging technology only. It is cost-driven, and it is well understood. But that does not mean there is no room for innovation. At IMEC, for example, we look into developing 3D-WLP stacks using wafer-level packaging (WLP) technologies such as redistribution, flip-chip bumping and through-silicon vias. In such stacks, we combine heterogeneous functions, such as logic, memory, and analog sensors.
But 3D promises to be more than stacking 2D chips by connecting bond pads from one die to the other. Tighter 3D integration will be necessary to keep doubling the density of designs every 2 years, in line with Moore’s law. This requires splitting the IC design itself into multiple stacked physical layers, which we call 3D-stacked ICs or 3D-SIC. And eventually, we could think of stacking and connecting chips at the level of transistors, arriving at a 3D-IC. Research and industry are already tackling the technical aspects of 3D-SIC/IC. One challenge is making small enough vias with high aspect ratios. Another one is handling wafers and chips thinned well below 50µm, at which level the chip may curl up, and show microcracks that influence the transistors’ behavior. And when you finally have those ultra-thin chips with micrometer-sized vias, you have to find a way to position the vias of one chip precisely on the landing pads of the second chip, which is no trivial problem.
The really hard part of 3D-SIC/IC technology, however, will be the design. The use of dense through-silicon vias allows designs that solve some of the interconnection problems of 2D designs. But at the same time, the complexity of 3D is many times that of 2D, involving issues such as testability, yield, quality, heat management, signal integrity, and choice of approach. IMEC is one of the only centers that combines research on advanced 3D technology and research on 3D design. IMEC’s 3D industrial affiliation program (IIAP) targets 3D-WLP, 3D-SIC, and 3D design. It allows industry players to join our research efforts, sharing the costs, risks, talents, and IP of 3D research.
One task within the program is to demonstrate the process steps of 3D integration, and to measure and improve the reliability and yield of real silicon implementations of 3D modules. At the same time, we will draw up predictive design rules and models for the 3D technology community.
And to exploit all benefits of 3D technology, design and technology options should be optimized together. Therefore we are looking into path-finding methods, comparing the relative pros and cons of the many technology and design options.
Another issue is that 3D needs classification and roadmapping, as we learned from mainstream CMOS. The industry is currently looking at too many options and paths, and the tools and equipment suppliers can no longer see the wood for the 3D trees. For this reason, IMEC will organize a workshop in Taiwan, later this year. This meeting will bring major 3D players round the table to discuss 3D issues and options, and to agree on conventions and roadmaps.
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