The fact that our industry has been able to satisfy these demands, so far, is beyond remarkable. Much is attributable to progress in line with Moore’s Law, putting vastly more computing power onto ever-shrinking dies, with the related effects on power-supply sizes, signal speeds, and interface bandwidth. In today’s post-Moore era, maintaining the trend demands innovation in every aspect of the system, from 3D chip design to save silicon floorspace to PCB fabrication and component packaging.
Packaging
Packaging serves today’s manufacturing models. It’s the medium that enables the various component parts – including processors, power semiconductors, passives, etc – to be made in different factories by companies with different specialisms and configured and integrated by organisations that have their own competencies, like system design and, ultimately, production.
In the post-Moore era, component packaging is as urgent a target for miniaturisation as any other aspect of the system. Minimising packaging overheads not only helps build smaller systems but also contributes to performance improvement by reducing associated parasitic effects, like electrical resistance that causes power loss and self-heating, and thermal resistance that impairs dissipation.
In an ideal world, we want packaging to go away, and there is precedent for this. It’s what FPGA manufacturers have been doing for years by making it possible for designers to absorb the functions otherwise implemented in multiple discrete ICs into one single – albeit relatively large – device. Direct-bond assembly employed in power modules is another example, increasingly prevalent with the rapid adoption of electric drive into today’s vehicles. In addition, the case is frequently made for embedding passive components such as decoupling capacitors directly in PCBs. This can, potentially, save space and enhance reliability, although the possibility has been discussed for some time without becoming reality. It remains an innovation we await eagerly and may see in the near future as innovations in materials science and fabrication processes take us closer to a solution.
Having wished packaging into non-existence, in the real world it is, of course, incredibly important and is a key area for research to drive ongoing miniaturisation; especially now that advancing chip lithography, alone, is not able to deliver the progress we need. Its growing importance is underlined by the fact that foundries and integrated device manufacturers (IDMs) are beginning to drive innovations in this area. Historically, it has been the unchallenged territory of outsourced semiconductor assembly and testing (OSATs) or semiconductor packaging, assembly, and testing (SPATs) companies.
