Zum Inhalt springen
EPP Europe
  • News
  • Products
  • Applications
  • Technology
  • Semiconductor
  • Inspection
  • Company News
  • Events
EPP Europe
  • Technology
  • Inspection (AOI/AXI)
  • Semiconductor Packaging
  • Company News
  • Products
  • Trade Shows & Events
    EPP Europe Newsletter
    The most important electronics-manufacturing news delivered to your inbox.

    Info

    • Impressum
    • Datenschutz
    • Barrierefreiheit
    • Datenschutzeinstellungen

    Kontakt zur Redaktion

    EPP EuropeKonradin Mediengruppe
    Ernst-Mey-Str. 8, 70771 Leinfelden-Echterdingen

    E-Mail: redaktion@konradin.de
    Folgen Sie uns
    EPP Europe
    © 2026 EPP Europe
    Startseite/Semiconductor-packaging/Artikel
    UTAC Announces New High Output Copper Clip DFN
    Bildquelle nicht angegeben
    Semiconductor-packaging

    UTAC Announces New High Output Copper Clip DFN

    UTAC Holdings Ltd. (UTAC), a global semiconductor test and assembly services provider, is announcing a punch copper (Cu) clip packaging solution for power
    Veröffentlicht
    10. Juni 2022
    Lesezeit
    1 Minute
    Rubrik
    Semiconductor-packaging

    There is significant capacity of MOSFET assembly and test. But UTAC’s in-line / modular assembly process provides a very cost effective assembly and test solution.

    The copper clip technology not only provides better electrical performance compared with wire bond packages but also provides enhanced thermal path within the package, ensuring that the MOSFET runs cooler, thereby enhancing reliability and enabling greater power densities. The compact MOSFET Cu clip maintains the common package industry footprint of 5 x 6 mm.

    Dr. John Nelson, President and CEO, UTAC comments, “Packaging of discrete devices plays a key role in the performance of power solutions. Our new discrete Cu clip line will provide a cost effective solution for our customers.”

    He continued “Alongside this we are setting up thin wafer handling (down to 2 mil) for PQFN56 packages and we intend to develop a 10 mil Cu clip for this technology to support further advances.”

    Mehr aus Semiconductor-packaging

    Weitere aktuelle Artikel aus der Rubrik Semiconductor-packaging.

    Alle Semiconductor-packaging-Artikel
    Nanoscribe Expands Photoresin Portfolio for Micro-Optics Fabrication via Two-Photon PolymerizationFoto: Brecht Corbeel / Unsplash
    Semiconductor-packaging

    Nanoscribe Expands Photoresin Portfolio for Micro-Optics Fabrication via Two-Photon Polymerization

    11. November 2026

    Nanoscribe has detailed its range of photoresins engineered for Two-Photon Polymerization (2PP) and Two-Photon Grayscale Lithography (2GL), targeting high-precision micro-optics manufacturing on silicon, glass, and…

    Canon Launches FPA-6400ES6a KrF Lithography System with 400 Wafers-per-Hour ThroughputFoto: Canon Europe (semicon)
    Semiconductor-packaging

    Canon Launches FPA-6400ES6a KrF Lithography System with 400 Wafers-per-Hour Throughput

    10. November 2026

    Canon has announced the FPA-6400ES6a KrF scanner for semiconductor lithography, combining a throughput of 400 wafers per hour with industry-leading overlay accuracy of 4.0 nm and the ability to handle wafer warpage of…

    Fabmatics absorbs SCI business activities under unified brandFoto: Ludovico Ceroseis / Unsplash
    Semiconductor-packaging

    Fabmatics absorbs SCI business activities under unified brand

    6. November 2026

    Fabmatics has integrated the business activities of SCI under the Fabmatics brand, consolidating the acquired expertise within its semiconductor automation portfolio.

    Entegris and Kioxia Expand Partnership on Materials Innovation for Next-Gen 3D Flash MemoryFoto: Louis Reed / Unsplash
    Semiconductor-packaging

    Entegris and Kioxia Expand Partnership on Materials Innovation for Next-Gen 3D Flash Memory

    6. November 2026

    Entegris and Kioxia are deepening their strategic partnership to co-develop materials and process technologies for future BiCS FLASH 3D NAND architectures, using AI, digital-twin modelling and experimental validation at…

    ← Zurück zu Semiconductor-packagingZur Startseite