Goepels’s debug hardware for IEEE 1149.1/JTAG circuits features a logic probe, to extend the traditional boundary-scan by additional logic information. The probe detects various modes of static and dynamic input of weak logic levels, to simplify the verification of designs. The evidence of BS structures on chip level and the related BSDL files can be automated by emulation.
“The Boundary Scan Probe is another corner stone on our way to find solutions for the extended Boundary Scan test,” declares Bettina Becker, GOEPEL electronic’s marketing manager, and adds: “The new technology makes it possible to improve the efficiency of diagnostic debugging was well as to simplify the structural verification of Boundary Scan designs.”
The probe is compatible with all BS controllers of the company, and supported by the software package Cascon. The upgraded development environment Cascon V4.03 in particular increase the efficiency of in-system programming of Flash memories as well as the verification of test procedures. The automated flash program generator handles memories of unlimited size (64, 128, 256 Mbit, etc.), and bus width (serial, 8bit, 16 bit, 32 bit, 64 bit, etc.) individually or cascaded. This flexibility is supplemented by the support of several interfaces (single ended, open collector, bi-directional, etc.) and flash-specific programming modes, so, the tool is ready for next-generation devices. The files are hardware-independent and are compatible on all BS controllers of the company. The vector-browser tool provides hierarchical visualization of net and pin levels, using the principle of scalable tree-type structure. Faulty pin levels can be viewed in color as well as selectively viewed.
EPP EUROPE 479
