As IC designs progress to more advanced nodes at 5nm and below, they become increasingly susceptible to manufacturing variations that can create defects and slow yield ramp. At these geometries, traditional failure analysis (FA) methods can require weeks or months of laboratory effort to investigate. The new tool addresses this problem by rapidly providing transistor-level isolation for scan chain defects. For advanced process nodes where yield ramp heavily relies on chain diagnosis, the new software can boost diagnosis resolution by more than 1.5x, reducing the need for costly extensive failure analysis cycles.
“Tessent Hi-Res Chain represents a major leap forward in our ability to rapidly identify and address yield-limiting factors in advanced IC designs,” said Ankur Gupta, vice president and general manager of the Digital Design Creation Platform division, Siemens Digital Industries Software. “By providing unprecedented accuracy and resolution in defect isolation, we‘re empowering our customers to accelerate their yield ramp and improve time-to-market for cutting-edge semiconductor products.”
By correlating design information and failure data from manufacturing tests with patterns from Tessent automatic test pattern generation (ATPG), the Hi-Res Chain transforms failing test cycles into actionable insights. The solution employs layout-aware and cell-aware technology to pinpoint a defect‘s most probable failure mechanism, logic location, and physical location.
