Both processors have been specifically designed for use in AIS units utilising Limiter-Discriminator RF architecture. Both are half-duplex in operation, comprising two parallel Limiter-Discriminator Rx paths and one I and Q or two-point modulation Tx path, configurable for both marine AIS or DSC operation.
The two have identical core functions. One provides maximum integration with the inclusion of two on-board auxiliary RF synthesizers. The other comes without RF synthesizers, offering maximum RF system flexibility and the smallest foot-print package for designers wishing to separate baseband and RF operations.
Both devices push on-chip integration to new levels by performing signal modulation/demodulation and associated AIS functions, such as training sequence detection, NRZI conversion and HDLC processing (flags, bit stuffing, CRC generation and checking). Combined with the integrated Tx/Rx data buffers, the overall host microcontroller processing requirements are greatly reduced. Auxiliary DAC and ADC functions are provided to further simplify system hardware design, thus reducing overall end-product size and cost, which are major market drivers.
Both products utilize the company’s proprietary FirmASIC component technology. On-chip sub-systems are configured by a Function Image. This is a data file that is uploaded during device initialisation and configures the device’s function and feature-set. The Function Image can be loaded automatically from an optional external EEPROM or from a host microcontroller over the built-in C-BUS serial interface. The device’s features and functions can be enhanced by subsequent Function Image releases, facilitating in-field upgrades. Both devices operate from a single 3.3 V supply.
electronica, booth A5.201
EPP Europe 444
