The benefits offered by the JTAG Technology for debugging, testing and in-system programming are not limited to complex designs with many JTAG devices. Designs with only a few, even just one or two, JTAG devices can also greatly benefit from this technology during all stages of the life cycle. A toolset capable of handling even the most (very) complex boundary-scan designs, however, often is not economically feasible for a company that only uses a few JTAG devices in its designs. The package establishes a new class of test and device-programming tool-set that dramatically lowers the cost of entry for test and hardware engineers, while still offering the many traditional benefits of JTAG/boundary-scan alongside newer technologies like processor-controlled test.
The suite works with or without design netlist data and can be used to test interconnects (from individual nets to an entire board), logic clusters, memories and more. Studio also includes device programming features that support JAM/STAPL and SVF data formats for CPLD and [FPGA] configuration PROM programming. It can be further used to program flash and serial PROMs. Low-cost options for accessing the debug modes of ’processor cores allows cut-price access to techniques known variously as Processor Controlled Test and JTAG Emulation Test. A dedicated, USB-powered, TAP interface/controller with programmable thresholds is also supplied as part of the Studio system.
