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    Startseite/Semiconductor-packaging/Artikel
    Indium Corporation to Address AI Packaging Challenges at SEMICON Taiwan 2026
    Foto: Indium Corporation
    Semiconductor-packaging

    Indium Corporation to Address AI Packaging Challenges at SEMICON Taiwan 2026

    Senior Technical Manager Jason Chou to present material solutions spanning microbump wafer bumping, mid-temperature solder pastes and thermal interface materials for high-performance computing
    Veröffentlicht
    03. September 2026
    Lesezeit
    2 Minuten
    Rubrik
    Semiconductor-packaging

    Indium Corporation has announced that Jason Chou, Senior Area Technical Manager at its Taiwan facility, will deliver a technical presentation titled 'Material Solutions for AI Industry from Packaging to System Assembly' at SEMICON Taiwan 2026 (2–4 September, Taipei). The session is scheduled for 4 September, 13:20–13:40 CST, at Booth 12416.

    The presentation addresses a set of interconnected engineering problems that have become central to advanced semiconductor packaging as AI workloads drive chip power densities to levels that stress conventional assembly processes and materials. Chou will cover the full chain from integrated circuit level to complete system assembly.

    Among the solutions highlighted are high-performance flux materials developed for microbump wafer bumping and Chip-on-Wafer (CoW) processes. CoW integration is increasingly adopted in AI accelerator and HPC packages where multiple dies are stacked or bonded at fine pitch, placing stringent demands on flux activity, residue behaviour and compatibility with subsequent underfill or molding steps.

    Indium Corporation will also present mid-temperature solder pastes formulated to mitigate Head-in-Pillow (HiP) and Non-Wet-Open (NWO) defects. Both defect types are a persistent concern in advanced BGA and package-on-package assembly, particularly where warpage during reflow causes incomplete joint formation. Mid-temperature alloy systems reduce peak thermal exposure, thereby limiting warpage-induced risk without sacrificing joint reliability.

    The third materials category covered is thermal interface materials (TIMs) for high-performance computing chips. As AI processor TDPs continue to rise — pushing into ranges that challenge conventional polymer-based TIMs — low thermal-resistance indium-based or specialised composite TIM solutions are attracting renewed attention from chip and system integrators seeking to maintain junction temperatures within specification.

    For European electronics manufacturers and their supply chains, Indium Corporation's presence at SEMICON Taiwan is relevant for several reasons. European EMS providers and ODMs supplying AI infrastructure hardware source advanced packaging materials globally, and materials qualified at the wafer-level packaging stage in Taiwan frequently enter European assembly lines downstream. Understanding flux and solder paste performance at microbump scale, as well as TIM selection criteria for HPC modules, is therefore pertinent to process engineers working on server, edge AI and industrial computing platforms in Europe.

    Indium Corporation, founded in 1934 and headquartered in Clinton, New York, supplies solders, fluxes, brazes, sputtering targets, TIMs and specialty metals including indium, gallium and germanium to the global electronics and semiconductor industries. Jason Chou holds chemistry degrees from National Cheng Kung University and National Tsing Hua University, Taiwan, and provides technical support to semiconductor-sector customers from the company's southern Taiwan base. Further information is available at indium.com.

    Quelle: Indium Corporation – https://www.indium.com/press-releases/indium-corporation-expert-to-present-ai-packaging-and-high-power-consumption-solutions-at-semicon-taiwan/

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