“With our new system tools we have completely closed the gap between classic Boundary Scan testers and conventional JTAG flash programmers”, Thomas Wenzel, Goepel electronic’s managing director, gladly announces. “Now our customers are able to define their individual ideal programming and test strategy for each kind of flash application, regardless of whether it is embedded in a system-on-chip (soc), single chip or complex flash cluster – implemented on basis of a unified JTAG/Boundary Scan system.” A new ISP tool is the Automatic On-Chip Flash Generator. It is based on the revolutionary streaming technology VarioTAP, introduced earlier this year. The tool is able, for instance, to program MCUs with integrated Flash via the JTAG TAP (Test Access Port). Thereby, required information is read from a respective VarioTAP PI model, and an executable script is generated in the native system language Caslan. The flash size is unlimited. The generator also supports Multi-TAP/Multi-Core applications as well as Scan Router. That’s why on-chip flash programming procedures can easily be combined with other ISP and test routines to a complete sequence. Also the Automatic Flash Program Generator (AFPG) for flash programming via Boundary Scan was enhanced. The most significant innovation is the ability to identify and program flash clusters, isolated in terms of access, by non Boundary Scan buffers. Several buffers may be cascaded within the circuitry.
www.goepel.com & www.goepel.co.uk
EPP Europe 466
