Zum Inhalt springen
EPP Europe
  • News
  • Products
  • Applications
  • Technology
  • Semiconductor
  • Inspection
  • Company News
  • Events
EPP Europe
  • Technology
  • Inspection (AOI/AXI)
  • Semiconductor Packaging
  • Company News
  • Products
  • Trade Shows & Events
    EPP Europe Newsletter
    The most important electronics-manufacturing news delivered to your inbox.

    Info

    • Impressum
    • Datenschutz
    • Barrierefreiheit
    • Datenschutzeinstellungen

    Kontakt zur Redaktion

    EPP EuropeKonradin Mediengruppe
    Ernst-Mey-Str. 8, 70771 Leinfelden-Echterdingen

    E-Mail: redaktion@konradin.de
    Folgen Sie uns
    EPP Europe
    © 2026 EPP Europe
    Startseite/News/Artikel
    Zero-defect testing requirements for automotive electronics
    Foto: Laurens van der Drift / Unsplash
    News

    Zero-defect testing requirements for automotive electronics

    Cadence Design Systems, Inc. and Advantest Corporation have announced a collaborative partnership to deliver a methodology for zero-defect testing of
    Veröffentlicht
    14. März 2007
    Lesezeit
    2 Minuten
    Rubrik
    News

    Diverging sharply from their analog roots, automotive manufacturers today are driving their suppliers to advanced semiconductor technology in support of high-value automotive applications. They are also demanding just-in-time delivery and, to reduce their risk, zero defects. This combination of factors requires a faster, more accurate testing methodology to achieve the same high quality and low risk. Using Advantest’s automated test equipment (ATE) platforms, the collaboration combines traditional analog part average testing (PAT) techniques with small delay defect detection capabilities of the Cadence Encounter True-Time Test software to produce a new generation of single-pass test methodologies for zero-defect testing of digital parts. Cadence Encounter Test, a key component of the captive Encounter digital IC design platform, delivers an advanced test solution from RTL to silicon. Key technologies include Power-Aware ATPG methods to reduce power during test, test-data compression to lower cost of test, true-time delay test to detect small delay defects. In combination with Encounter Diagnostics for accelerated yield ramp, these technologies provide the highest quality of shippable silicon. “The Cadence Encounter True-Time Test ATPG will allow us to create a single-pass and fully integrated test methodology for zero-defect digital designs, increasing product quality and reducing time to market and risk”, said Shinichiro Umeda, Senior Vice President of Software Development Group at Advantest. “It’s a focused collaboration to provide specific benefits to the automotive industry, but will be applicable elsewhere as well.” “Although this is a deep collaboration, from the standpoint of the automotive design chain, it has important benefits not just for Cadence and Advantest, but for our customers, their customers, and ultimately the individual car buyer”, said Sanjiv Taneja, Vice President of R&D for Encounter Test at Cadence. “By ensuring the quality of digital electronics in automobiles, we ensure the reliability of a dozen or more major components in every new car.”

    www.cadence.com

    https://www.advantest.com/

    Mehr aus News

    Weitere aktuelle Artikel aus der Rubrik News.

    Alle News-Artikel
    Microtronic Takes on Distribution of iRaptor EYE Thermal Profiler in GermanyFoto: Laurens van der Drift / Unsplash
    News

    Microtronic Takes on Distribution of iRaptor EYE Thermal Profiler in Germany

    9. November 2026

    German distributor Microtronic has announced it will represent iRaptor LDA and its EYE thermal profiler in Germany. The Portuguese developer's system extends beyond conventional 2D time-temperature profiling by…

    Indium Corporation Presents Solder Materials Research at SMTAI 2026Foto: Indium Corporation
    News

    Indium Corporation Presents Solder Materials Research at SMTAI 2026

    29. Oktober 2026

    Indium Corporation is fielding five specialists at SMTA International 2026 to present new findings on solder paste rheology, BGA ball alloy selection for lower-temperature reflow, and the effect of print gap on paste…

    KYZEN to Present AQUANOX Aqueous Cleaning Chemistries at SMTA International 2026Foto: Vishnu Mohanan / Unsplash
    News

    KYZEN to Present AQUANOX Aqueous Cleaning Chemistries at SMTA International 2026

    16. Oktober 2026

    KYZEN will exhibit its AQUANOX line of aqueous electronics cleaning chemistries at SMTA International, October 27–29, 2026, highlighting prolonged bath life as a process efficiency and cost-reduction lever for…

    Fuji America and Cybord Partner to Integrate Visual AI Component Inspection into SMT LinesFoto: Cybord
    News

    Fuji America and Cybord Partner to Integrate Visual AI Component Inspection into SMT Lines

    29. August 2026

    Fuji America Corporation and Cybord have announced a strategic partnership to embed AI-powered component analytics directly into SMT production lines, enabling 100% real-time inspection of electronic components during…

    ← Zurück zu NewsZur Startseite