It starts with two programs 3D-stacked IC (3D-SIC) and 3D systems-on-chip (3D-SoC). The 3D-stacked ICs – characterized by short high-density interconnects between the chips, showed advantages concerning power and performance, and the ability to interconnect chips with divergent process flows. The Si-through connections are realized during the foundry process, between the frontend and backend of line. The 3D-SoC program points to heterogeneous integration of systems in which circuit blocks (tiles) on a die are interconnected to blocks on another die after passivation, without passing through the regular chip I/O pads. Each of these dies may be manufactured using a different technology, realizing 3D-connections after the Si-foundry process (post-passivation), using wafer-level-packaging (WLP) technologies. The target dimensions of the through-Si connections are diameters down to approximately 25µm and pitches down to 50µm, for wafers thinned down to 200 to 50µm. The completion of low-resistance, low-capacitance and low-cost through-wafer interconnects is a major target for the 3D-SoC technology design. Special attention is given to through-Si via reliability and RF-through applications.
EPP EPE 410
