To say it bluntly, none of all these self-claimed business pundits and consortia gurus are among an elite who can predict the future in semiconductor business. Expert opinion came in all shades of dark to light-gray. Some arrows are pointing up, others still down. “Given the severity of business conditions in the overall economy”, Semi CEO Stanley Myers states, alluding to the U.S., “it comes as no surprise that the consensus forecast shows another drop in the worldwide market for capital equipment in 2002.” But for next year, prospects are good, Myers optimistically promises. A tad even more optimistic, if creative in his wording, is James Morgan of Applied Materials: “The first phase of the recovery is beginning. There is a shortage of production capacity at 0,13µm.” First phase, according to him, is when capital spending isup and fabs are running at 90% utilization. Where does he see that now?
Enough of the lament, let’s do the numbers – which are difficult to sort out anyway. First the really bad news: sales of assembly and packaging equipment are now expected to decline by 23% this year. Semi originally forecasted a minus of only 3 %. (To illustrate what’s happening in Central Europe: the German VDMA, Special Group Productronic, has initially expected an equipment decline of about 21%, and now gets figures back from its members shouting that we are down by 50%, and some even worse). Worldwide equipment bookings in July, declares Semi researcher Dan Tracy, “reflect renewed questions about the robustness of the economic recovery”. The worldwide book-to-bill ratio for capital equipment slipped back to 1.16 in July, down from 1.26 in June and May. A glimmer of hope: orders ($1.176bn) were up 50% compared to those in July 2001, but billings are still down by 17%. Nonetheless, at Kulicke & Soffa for example, there is a faint indication of recovery: an uptake in orders for leading-edge applications. Apparently, the old saga is still valid: first comes the buying for technology needs, followed by manufacturing capacity.
Not everybody subscribes to this carefully balanced view. VLSI Research pegs the July book-to-bill at a low 0.77, after 1.15 in June. Various banking analysts are even more dim and divergent, depending on their understanding of and access to the industry. As one of the possible consequences, chip-fab outlays will drop further this year. The question remains: just by 2% (estimated by Merrill Lynch) or by a whopping 20% (predicted by usually reliable Gartner Dataquest)?
Is the ominous double-dip recession grabbing us by the tail? At least in the U.S. that seems to be the case as shown by slackening consumer spending. Also in Scandinavia and middle Europe, there is an exceptionally bad mood in trade, industry and banking business. And this isn’t an encouraging momentum for overwhelming “consumerism” in techno-products, needing some kind of electronics. Not to be forgotten is that after the burst of the business bubble, formed by the new economy and telecommunications hype and the year 2k computer surge, on the stock exchange dramatically loses were also experienced. Many normal share holders (setting aside money for retiring or dire times this way) seeing their deposit account drying up like morning dew in the sun has caused a creeping feeling of increasing poverty. Not exactly encouraging purchasing of another car, dishwasher or whatever.
On to the technological trends apparent at Semicon West, which was a rather quiet affair devoid of any really uplifting news, but 1500 exhibitors were there and an estimated 50,000 attendees showed up. Yet despite the prevailing gloom, one thing is sure: once the industry gets out of its present slump, hopefully by 2003/2004, it will be a different business. Wafer-level packaging, flip chip, 3D/stacked die assemblies, the advanced packages are heading for mainstream high-volume markets. Tessera’s MicroZ ball-attached memory package contains two dies and builds on their MicroBGA package, offering scalable memories in low-cost layout. Another innovative step: Amkor’s stacked CSP, also containing two or three dies. Total height of this assembly: 1 or 1.7mm – needing wafer thinning down to 75µm. Similar ideas are emanating from semiconductor manufacturers worldwide, making this a sound trend in packaging. Micron basked in the glow with its 256Mb SDRAM ina wafer-level/chip-scale package.”That’s a very important announcement,” thinks market researcher Jan Vardaman of TechSearch International. “Because if DRAMs were to be packaged at the wafer level, that would increase volume dramatically. Wire bonding is still the workhorse of the industry.” But production volume is all that is needed now to accelerate the shift from wire bond to WLP at the low end, and to flip chip at the high end in terms of performance and I/Os.
Another place for spotting assembly trends: the IEMT (International Electronics Manufacturing Technology) Symposium of the IEEE CPMT (Components, Packaging and Manufacturing Technology) Society, held across the street from the San Jose Convention Center. Topics were, besides WLP, flip chip and ball-grid arrays and developments in wire bonding. And entrepreneur Scott Kulicke was honored, as customary at U.S. business events, with an award for transforming his firm into a “global leader in semiconductor interconnecting technologies”.
If WLP marks another significant path to cost reduction in chip manufacturing and, at the same time, will “spur the recovery” as Franz Richter of Suss Microtech sees it, there is the question of who will fund its R&D, and who will roadmap its orderly progression. “Seems a good question”, answers TechSearch’s Vardaman, “I’m not sure. That’s a big concern.” Fact is that some chipmakers and OEMs want to get out of manufacturing – all issues of packaging, assembly and interconnect. They want to contract as the outsourcing movement gains speed. Consequently, frontend as well as backend are heading for Taiwan and even farther, to China.
So, where will be the locus of backend R&D in the future? Within industry consortia, you guessed it, as they already exist in the frontend arena: Sematech, Selete, among others. It turns out that there is not only one such backend consortium but already two of them – battling it out for attention. First, there was SECAP (Semiconductor Equipment Consortium for Advanced Packaging) formed back in 2000 by Suss Microtech, Semitool, Image Technology, Balzers/Unaxis, forming a team with Fraunhofer IZM, Berlin/Germany. Tutorials and demos were initial activities. Since February 2001, SECAP has been able to show electroplated 300mm wafers, fully functional, with 70µm bumps, mask patterns and full-face seed layers. Just recently, Infineon and ASE have come aboard.
Now there is competition, and it shows full force: the APiA (Advanced Packaging and International Alliance). It was set up on December 2001 by founding members August Technology, Casio Computer, Dainippon Screen, EBNA, K & S, Ultratech Stepper and, again, Unaxis/Balzers. Recent new members are the Albany NanoTech research facility, Dynaloy, EKG, Excelerate Tech, HD Microsystems, Heller Industries, Sikama Industries and Adept Technology. Reportedly, SECAP is a step ahead. Later this year, it will install a 300mm line for electroplated bumping at Unitive, Hsinchu/Taiwan, and demonstrate volume processing. APiA is planning a 200mm line with ACE in Shanghai/China. Collision or competition – whatever the two rivaling consortia are on to, they are good for the industry, thinks Vardaman. “It will bring people involved in frontend processing into the backend. It’s getting more difficult to distinguish between the two.” Briefly: fabrication, assembly and test are coming together in a concerted effort at decreasing cost. Werner Schulz/Gerhard Wolski
