Speaking at the Gartner Dataquest semiconductor industry briefing, Smith said that semiconductor vendors must design complete systems including embedded software, and move up to electronic system level (ESL) design. Design for manufacturing (DFM) concerns may bring about the end of the customer-owned tooling (COT) model and turn foundries into ASIC vendors, he said.
“Contrary to popular opinion, 65 nm is turning out to be much easier to design than we thought,” said Gary Smith. “What it will do is change the semiconductor business picture dramatically.” Semiconductor vendors, said Gary Smith, will be forced to either upgrade their design capacity to meet competitive pressures, or downgrade their design capacity to meet cost pressures. Because companies did too much disaggregation in the 1990’s, a wave of re-aggregation is coming, he said.
With System-on-Chip (SoC) design, Smith said, embedded software has become a major competitive design component. For EDA providers, it’s an area of needed focus. “Software is by far the number one issue we have in design,” he said. At 65 nm, Smith commented, there is a major post-GDSII DFM design effort. With the need for resolution enhancement techniques, semiconductor design firms should consider bringing mask-making back in house, he said. Furthermore, for DFM layout, compact process models are an “absolute must,” but foundries won’t give them to more than a handful of trusted, major customers.
Without a secure, compact process model, IC layout will be brought in-house, spelling the end of the COT model, Gary Smith said. He noted that foundries are starting to provide an “ASIC like” business model to their customers, and said that some “upper mainstream” companies have stopped doing IC layout and are passing designs off using a gate-level netlist. What these companies really need to consider, in his opinion, is RTL handoff.
Power users must continue to hold their design and silicon edge, Smith said, but they also must realize that the key to the new semiconductor market is applications knowledge. Thus, they cannot complete embedded SoCs without significant software content. “The ‘S’ in SoC stands for system, but the semiconductor guys don’t understand that,” Smith said. “You are designing systems. That means that ESL will bring an entirely new approach to the market.”
You really think that 65-nanometer design will change the entire semiconductor industry business? Could you state that more precisely?
As we continue to decrease our silicon geometry, we need more and more silicon information to produce yielding, or even working, designs. This is the DFM crisis. In order to take advantage of 65 nm we really need access to a Compact Process Model. Unfortunately, that model is a looking glass into the process. Since less and less semiconductor vendors have the ability to develop an advanced process, the idea of someone reverse engineering your process is not a good thing. This means we either must develop a “Secure” Compact Process Model or keep the DFM work in-house. That is what we see happening now. The COT model is only available to a few large customers. The rest are moving to some form of the ASIC model whether with ASIC Vendors or the Foundries themselves. Along with that is the switch to the SoC market and ESL design.
How dramatical could this change be – would you be implying a business revolution?
The DFM issue is less of a revolution than a move back to the business models of the 1980s. The 1990s was the Cream Puff era for semiconductors. Everything was relatively easy. Now we´re back to working for a living again. SoC and ESL “are” a revolution. Semiconductor Companies are moving from component suppliers to system suppliers. The key today is applications knowledge and embedded software expertise.
Which capital investment will come up to the semiconductor industry and in which dimension? Could you evaluate that already?
The added investment today is in software development. That didn’t use to be our job. It surely is today.
Will capital investment in 65-nanometer design affect charges, profit and stock prices in a moderate or considerably extent?
I think people get hung-up on the expense side because they are looking at SoCs as components; they aren’t. If you compare SoC costs with how much it costs to build a comparable system with components, if you even could build such a system with components, I think the SoC cost would almost always be lower. People only talk about the consumer market having the volume to afford these new designs, and then you find the calculations used the mythical five dollar SoC. I don’t see Intel selling their processors for $ 5, so why would you expect any other SoC (and yes Intel’s processors are SoCs today) for $ 5? Throw in a 50, 500 or even a 5,000 dollar a piece price and the math comes out “much different”. (fan)
