As part of their long-standing strategic partnership, the two companies have mastered a task previously considered impossible, capturing tens of trillions of cycles over a span of just a few days by taking advantage of Siemens’ Veloce proFPGA CS scalable and performance-optimized hardware architecture and combining it with NVIDIA’s performance-optimized chip architecture.
“NVIDIA and Siemens are partnering in many areas, most recently in advancing hardware-assisted verification methodologies in general and FPGA-based prototyping in particular, to adapt to the verification and validation demands presented by highly complex AI/ML SoCs,” said Jean-Marie Brunet, Senior Vice President and General Manager, hardware assisted verification, Siemens Digital Industries Software. “Veloce proFPGA CS is addressing these challenges by combining a highly flexible and scalable hardware architecture with an advanced, easy-to use implementation and debug software flow, enabling customers to always have the optimal solution for single-FPGA IP validation as well as for multi-billion gate chiplet designs,” Brunet added.
“As AI and computing architectures grow increasingly complex, semiconductor teams require high-performance verification solutions to validate massive workloads and accelerate time to market,” said Narendra Konda, Vice President of hardware engineering, NVIDIA. “The integration of NVIDIA performance-optimized chip architectures with Siemens’ Veloce proFPGA CS enables designers to capture trillions of cycles in days, providing the scale needed to ensure reliability for the next generation of AI.”
Field-programmable gate array (FPGA) based prototype systems are fast and allow users to run pre-silicon verification workloads in a fraction of the time it would take to run the same workload in simulation or even emulation. However, today’s AI/ML designs are demanding even more, in part due to the chip complexity and in part due to the software complexity.
To scale to these industry demands, meet time-to-market and align to reliability requirements, the ability to run trillions of design cycles in a short amount of time is now critical. Traditional verification tools like simulation and emulation do not scale beyond running millions, or best case a few billion cycles within a reasonable and practical amount of time.
