Siemens Digital Industries Software has announced the introduction the Tessent multi-die software solution, which helps customers dramatically speed and simplify critical design-for-test (DFT) tasks for next-generation integrated circuits (ICs) based on 2.5D and 3D architectures. The company says the technology paves the way for mainstream adoption of 3D ICs.
As demand for smaller, more power efficient and higher performing ICs continues to challenge the global IC design community, next-generation devices increasingly feature complex 2.5D and 3D architectures that connect dies vertically (3D IC) or side-by-side (2.5D) so that they behave as a single device. However, these approaches can present significant challenges for IC test, since most legacy IC test approaches are based on conventional two-dimensional processes.
To address these challenges, Siemens has introduced Tessent multi-die software – which it says is the industry’s most comprehensive DFT automation solution for highly complex DFT tasks associated with 2.5D and 3D IC designs. The new solution works seamlessly with Siemens’ Tessent TestKompress Streaming Scan Network software and Tessent IJTAG software, which optimize DFT test resources for each block without concern for impacts to the rest of the design, thereby streamlining DFT planning and implementation for the 2.5D and 3D IC era. Using the new multi-die software, IC design teams can rapidly generate IEEE 1838 compliant hardware featuring 2.5D and 3D IC architectures, the company explained.
“IC design organizations are seeing dramatic spikes in IC test complexity due to the rapid adoption and deployment of designs featuring densely packed dies in 2.5D and 3D devices,” said Ankur Gupta, vice president and general manager of the Tessent business unit for Siemens Digital Industries Software. “With Siemens’ new [m]ulti-die solution, our customers can be ready for the designs of tomorrow, while slashing test implementation effort and simultaneously optimizing manufacturing test cost today.”
In addition to supporting comprehensive test for 2.5D and 3D IC designs, the new software solution can generate die-to-die interconnect patterns and enable package level test using the Boundary Scan Description Language (BSDL). Furthermore, it supports integration of flexible parallel port (FPP) technology by leveraging the packetized data delivery capabilities of the company’s TestKompress Streaming Scan Network software. Introduced two years ago, this software decouples core-level DFT requirements from the chip-level test delivery resources. This enables a no-compromise, bottom-up DFT flow that can dramatically simplify DFT planning and implementation, while reducing test time up to 4X.
“As the limits of traditional 2D IC design approaches become increasingly clear over time, more design teams are leveraging the power, performance and form factor advantages that 2.5D and 3D IC architectures can deliver. But deploying these advanced schemes in new design starts without first establishing a DFT strategy that acknowledges the inherent challenges these architectures present can raise costs and undermine aggressive timelines,” said Laurie Balch, president and research director for Pedestal Research. “However, by evolving DFT technology to keep pace with the rapid adoption of multi-dimensional designs, EDA vendors can play a key role in further enabling global, mainstream adoption of 2.5D and 3D architectures.”