IMEC, a leading European independent nanoelectronics and nanotechnology research institute, will present 17 papers together with its core partners at the IEEE International Electron Devices Meeting on December 11–13, 2006 in San Francisco.
This record number of papers at one of the world’s leading conferences on semiconductor technologies showcases the success of this institute’s global R&D efforts to create solutions for (sub-) 32 nm scaling.
Several advances will be reported in the scaling of logic technology options. For extending bulk CMOS into the 45/32 nm nodes, the research center has developed an alternate integration process for its FUSI technology that is more manufacturing friendly without the need for a CMP (chemical mechanical polishing) step. It is based on using a planarizing resist and etch-back to open the FUSI gates.
On the alternate metal gate option, i.e. metal-gate first approach or deposited metals, the institute reports on MoOx as a promising pFET. Two papers on FinFET CMOS will be reported, demonstrating the impact of fin line-edge roughness on device characteristics, as well as the process technology to double or quadruple the fin density per area. Beyond silicon as substrate, the research establishment will demonstrate a short channel Ge pMOS device built with Si-compatible process techniques.
The research institute will present several results on reliability both in the field of 32 nm CMOS and Flash memories. A detailed electrical and failure analysis of the impact of using Cu contacts on the CMOS front-end yield and reliability will be reported. For the first time, NBTI (negative biased temperature instability) degradation experiments under AC conditions at frequencies up to 2GHz in SiON-based dielectrics will be presented. It will also be shown that ultra-fast progressive breakdown in HfO2/TaN/TiN gate stacks n/p-MOSFETs only occurs during substrate injection. A model to explain this polarity dependence will be presented.
“The results that will be presented at IEDM 2006 show that IMEC and its core partners have made significant advances in fundamentally understanding the bottlenecks in (sub-)32 nm scaling and developing the generic process steps, modules and devices,” said Luc Van den hove, Vice President Silicon Process and Device Technology at IMEC.
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