Goepel electronic, worldwide leading vendor of JTAG/Boundary Scan solutions compliant with IEEE1149.x, launched the Automatic Test Program Generator (ATPG) for true hierarchical test at the board level in the context of the Boundary Scan software platform System Cascon. The tool offers an unrivalled level of automation with the generation of board-centric boundary scan tests on the basis of true library models of conventional components. For the non-JTAG/Boundary Scan parts of the circuit, an enormously increased test quality with predictable fault coverage and pin level diagnosis is achieved without user modification. “The productivity of the generation of Boundary Scan test programs is nowadays significantly determined by the abilities of the tools in handling non-JTAG/Boundary Scan components. For this our new ATPG sets a whole new quality standard,” says Raj Puri, US Marketing and Sales Manager at Goepel electronic. “Due to the complete portability of the component test models independent from the design of the target board, the user no longer has to worry about the component tests, and constant model manipulations become redundant. The test program generation as a whole becomes more effective and safe for the customer.”
The basis of the hierarchical test concepts are component test programs that are a constant part of the complete system, and are administered by complete device libraries. These models are easily exportable to other stations. The test programs itself are defined by Source Code in CASLAN (CAScon LANguage). This specialised Boundary Scan programming language with more than 250 commands, enables algorithmic vector generation, adaptive fault diagnosis, interactive user communication, mixed signal test and file handling.
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