Flexible platform for optimization

MTQ Testsolutions, Amerang (Germany)

These small but intelligent boards are at the heart of embedded systems and distributed computing applications. Regardless of their end application, SM-B boards have a similar architecture: some mix of analog-to-digital or digital-to-analog conversion (or both) for input and/or output, a network interface, and a central programmable microcontroller that includes self-contained flash memory and often some RAM. The programmed contents of the flash memory define the overall function and operating parameters of the board.

Nowhere has the proliferation of SM-B boards been greater than in automotive applications, including remote sensing, mechanical actuation such as locking systems, LED interior and exterior lighting systems, control panels such as rear seat HVAC controls and numerous in-engine-compartment uses ranging from ignition control to controlling turn signals. In some cases multiple functions such as wiper motor and radiator fan controls have been combined onto a single board, reducing part count, complexity and total vehicle electronics cost. Almost all these boards are connected to the car’s central nervous system by a local interconnect network (LIN) bus.

The ever-growing demand for small ISP boards has spawned a cottage industry of third party suppliers with expertise in sensors, actuators and networked control applications. In these organizations project teams are responsible for overall design, manufacture and test strategies across a wide variety of end applications. While as noted above, SM-B boards are similar architecturally, each module design is sufficiently different that the design and manufacturing team requires great flexibility in how the board is programmed and tested. Let’s examine the impact of that flexibility requirement on manufacturing and test strategies and equipment.

Increasingly, SM-B boards are built in “multi-board panels,” which depending on the physical size of the individual board can range from eight to more than thirty boards per panel. During production, the panels are usually assembled, programmed, and tested as a single unit. The boards are then “de-paneled” once final test is completed. Panelization has proven to be a cost-effective way to provide high manufacturing throughput because fewer large panels can reduce the cost and risks of multiple handling steps involved with very small boards.

With a microcontroller and memory at the heart of each board, device programming requirements, especially the total time required to program and verify memory, become paramount. While pre-programmed chips are occasionally used, on-board programming (i.e., a “blank” ISP device is soldered to the board during assembly and then programmed in situ) is almost mandatory, not just to simplify inventory control of software versions, but also to allow programming of variables such as serial number, date code, and/or or measured parameters (e.g. calibration constants) unto an individual device. Further, the phase-change memories used in recent chip architectures are heat-sensitive, precluding programming prior to the chips experiencing the high temperatures of the reflow soldering process. The ability to simultaneously program the entire population of ISP memories on the panel is an essential element to achieving high throughput. Where older combinational testers used for on-board programming were limited to programming about four devices in parallel, modern on-board programmers can program several hundred chips simultaneously.

At the same time, the ISP programming system must be able to customize code for each device during this “gang” programming process to accommodate variables unique to each board. The device programming system must be able to call upon an extensive algorithm library for all popular device suppliers, as well as to be able to handle the encrypted code that many OEMs use to protect their intellectual property during the manufacturing process. The programming system itself needs be robust, well suited to the rigors of the high-rate-of-change manufacturing environment. This is one reason why most implementation teams reject the “dongle” architecture that has traditionally been used in comparatively more pristine product design labs.

Not unexpectedly, in-circuit test (ICT) is essential for multi-board panels with the additional requirement that the system can easily identify which board (or boards) has failed ICT not only for failure diagnostics to the individual board, but to prevent attempts by the system to further test or program that particular board in the panel. Because these are typically physically small boards with a fairly low component count, and because each board possesses “on-board intelligence” once it’s been programmed, ICT requirements are typically straightforward. Reduced ICT requirements are also due to improved component quality, higher manufacturing yields, and the “shifted” fault spectrum inherent in modern SMT processes. For example, the extensive vector digital test capabilities of traditional “big iron” testers are generally superfluous because digital vector “backdrive” is simply not required for today’s highly reliable digital chips.

Following the ISP device programming and verification step comes functional or operational test. Because the general architecture of small ISP boards is roughly similar, functional test will usually have common elements such as testing the network interface. Nevertheless, specific analog and digital test requirements will vary widely, calling upon facilities such as basic digital and analog signal generation and measurement ability – intrinsic capabilities already found in most in-circuit testers. In general, though, smaller boards mean simpler, less costly functional testing – and therefore a less costly test platform.

A successful manufacturing and test strategy needs to consider test and programming requirements separately – always with a view to optimizing test coverage while minimizing programming and verification times. In today’s resource-constrained reality, test strategy design is evolving from the outmoded “silo” organization of separate ICT, ISP programming, and functional test groups to an approach where the entire test and programming sequence for the panel is designed and implemented by a single team. Likewise, integrating ICT, on-board ISP programming/verification capable of programming multiple chips simultaneously, and final functional/operational test onto a single platform aligns well with this streamlined approach to test and programming organization.

Each project is sufficiently different and tact times will vary, but on-board ISP programming will often take longer than ICT or functional test. If the programming and test platform has parallel programming capability, ISP test and verification time can be minimized. For other projects, other combinations may make more sense. So, a flexible platform that allows optimization of programming and test protocols across a wide range of projects is highly desirable.

Multi-board panels affect other test platform requirements, as well. The tester must accommodate physically large panels up to 35 by 45 centimeters. The overall system must also have excellent noise immunity. The physical platform will be rugged and small—capable of being deployed easily to any location in the world. Standardized Windows-based systems, easily integrated into larger manufacturing network environments, are supplanting the proprietary operating systems of traditional “big iron” test systems.

Integrated test and programming platforms bear only superficial resemblance to the “combinational testers” of the late 20th century. Combinational testers were designed for the needs of the pre-microcontroller/memory era and sought to provide maximum test coverage of even the most obscure “corner case”. Today’s integrated test and programming platforms, on the other hand, seek to maximize test strategy flexibility and rapid physical reconfiguration. This flexibility allows engineers to play in the test and programming equipment “sandbox” in order to devise and implement optimum strategies for each board type as small ISP boards continue to proliferate.

Electronica, booth A1-668

Eine erfolgreiche Fertigungs- und Teststrategie für beispielsweise kleine Mikrocontroller-basierte Baugruppen muss die Test- und Programmieranforderungen gesondert betrachten, und zwar immer im Hinblick auf die Optimierung der Testabdeckung und die Minimierung der Programmier- und Verifikationszeiten.

Pour réussir, une stratégie de fabrication et d’essais pour les cartes à base de petits microcontrôleurs, à titre d’exemple, doit envisager à part les exigences des essais et celles de la programmation en s’attachant toujours à optimiser la couverture de code et à minimiser les temps de programmation et de vérification.