Packaging holds the key for the further implementation of Moore’s Law. The chances are better than ever that Germany and Europe will play an even more significant future role. In Research and Mechanical Engineering, their position is already well established. In the near future, Europe is also likely to be of greater importance as a production location for Electronic Packaging and especially for Wafer-Level Packaging.
For more than fifty years – specifically, since 1967 – Moore’s Law set the pace for innovation in the Chip Industry. The performance and complexity of Integrated Circuits doubled every 18 to 24 months. This principle now seems to be reaching its physical limits. In the single-digit Nanometer Range per Transistor, the costs of any further downsizing at the Wafer Level are simply prohibitively high. Dr. Michael Töpper, Fraunhofer IZM explains: ”Below 14 nm, Chip Production is simply no longer cost-effective.”
The logical conclusion: Developers must establish alternative leverage parameters to the downsizing of Wafer Structures. Electronic Packaging is an obvious choice. Real leaps in performance can be achieved here – for example, through the heterogeneous integration of a wide variety of components in a single package and the switch from two-dimensional structures to 2.5D or 3D Technologies.
The market is growing – for numerous reasons
The need for innovative Packaging Solutions is increasing for several reasons. Firstly, the Semiconductor market as a whole will grow on all levels – both within established mass applications and in new high-tech applications such as Autonomous Driving, Edge Computing and Artificial Intelligence. Strong growth is also anticipated due to rapidly increasing wireless applications (specifically 5G/6G) as well as – in the best case – billions of potential IoT/IIoT participants.
The division of labor in Chip Manufacturing is changing
As the key function for the implementation of Moore’s Law shifts to Packaging, the “classic” division of labour within Semiconductor Manufacturing is changing. Until now, specialised OSATs (Outsourced Semiconductor Assembly and Testing) or SPATs (Semiconductor Packaging, Assembly and Testing) have been in charge of Packaging. They are currently being challenged from two sides: The “foundries“ are planning to enter Packaging and have even become technology drivers here, IDMs (Integrated Device Manufacturers) are already active, as are suppliers from the upstream stages of the value chain as well as PCB Manufacturers or SMT Service Providers.
New Packaging technologies
However, there are ample opportunities for suppliers to differentiate themselves. This is because new technologies and processes are now available that enable a higher integration density without having to further increase the Transistor Density on the Wafer. This does not only involve a higher Packing Density and optimised Interconnect Technologies such as Soldering, Bonding and direct Connections. The structures also become three-dimensional, and the functional integration allows further miniaturisation of the Packaging while simultaneously increasing functionality.
Here is an overview of key trends and procedures:
Fan Out Wafer Level Packaging (FOWLP) and its further development Fan-Out Panel Level Packaging (FOPLP) permit very compact and cost-effective designs because they do not require a Substrate or Solder Contacts. Increasingly larger Panels are being used instead of Wafers, achieving additional cost reduction. This process is now being further developed with the aim of miniaturisation. Target markets include Packages for Smartphones, AI, Machine Learning and Autonomous Driving.
The copper-to-copper interconnects of Hybrid Bonding lay the foundation for 3D Chips such as Memory Cubes. This technology is used for Bonding Wafers and “stacking” Chips. TSMC, Intel and Samsung are already adopting this technology.
New Bonding Technologies in combination with, for instance, 2.5D approaches are breaking the ground for high-performance integration with additional components such as Graphics Chips, Memories, Antennas and RF Modules. This also includes Chiplets as a central trend that also simplifies chip development: You can use existing elements of ICs and only individual functional components require redesign. Intel already produces Chiplets on the Stratix platform. Samsung and AMD are working on them, Tesla is already using them, and TSMC are delivering complete chip “packages” to Apple.
The transition from the 2D arrangement of Transistors to a 2.5D or 3D design can significantly increase the Packing Density. 2.5D is already common, for example, in Chips for Data Centres, with “genuine” 3D Chip design in Memory Chips.
As is typical for Semiconductors and their Packaging, there are still many tasks to be solved on the journey from the development of such technologies to economical Series Production – both in Production and in Testing.
Investments in Packaging – on a European scale
Further developments in Packaging are primarily driven by the users. However the EU’s (funding) programmes are also a contributing factor. The desire for self-sufficient and strong value chains in Semiconductor Production has led the EU to increase the European share of global Chip Production from 10 to 20% by the end of 2030, and to provide funding for this specific purpose. Currently, domestic manufacturers such as Bosch as well as Asian (TSMC) and US (Intel) manufacturers are planning to build Chip Factories in Europe. And each new Factory can invest in new Packaging Solutions.
Opportunity for high-performance Plant Manufacturers and Suppliers
It is obvious that this situation offers opportunities for domestic Plant Manufacturers and their Suppliers. One such Plant Manufacturer is EKRA Automatisierungssysteme GmbH based in Bönnigheim. The company, which belongs to the ASYS Group, supplies Printing Systems for Wafer Level Packaging, which, among other things, apply Flux (Bumping). EKRA views the prevailing trend in Packaging in the further increase in Packaging Density, e.g. through the functional integration of Chips into Chiplets.
According to Product Manager Torsten Vegelahn, the establishment of new Chip Factories in Europe would eliminate an imbalance in the Industry: “German Mechanical Engineering is very well positioned in Semiconductor Production. Unfortunately, there are too few operators in Europe using these machines and manufacturing semiconductors locally. This is now being felt: The global supply chain is not resilient, logistics are unstable and costly. The consequence should be to set up manufacturing plants in EU countries with a high level of skilled workers.” This is exactly what will happen in the the years ahead.
Focus on growth
KoyYoung Europe GmbH also expects growth in Europe. As a specialist for Image Processing Systems, the company supplies systems for quality assurance in the Semiconductor Industry. They detect micro-cracks, chippings and foreign materials – for example, when Encapsulating LEDs.
Managing Director Harald Eppinger: “If the EU invests the planned 45 Billion Euros in Semiconductor Production by 2030, this will enable us to expand our business in Europe.” According to Eppinger, the European Chip Act will not only be an incentive for European companies to expand their production facilities, but also for Asian and American Semiconductor companies. “Then we can serve the customers we already supply in Asia within Europe too.” Overall, he sees good opportunities for the domestic plant manufacturers – providing one condition is met: “The industry must hurry to catch up with the competition and not miss the boat. If German companies position themselves correctly, we see enormous potential.”
From Dispensing to Printing
Christian Koenen GmbH in Ottobrunn also develops and manufactures Components for the Packaging Industry. Michael Zahn, Global Business Development Manager: “We supply global IDMs and OSATs with high-precision Printing Tools for processes such as Bumping and Die-Attach. We frequently jointly develop special printing processes and the relevant tools for them.”
According to Michael Zahn, the Packing Density will continue to increase, and the Manufacturing Processes will be faster and more reproducible. “That’s why our customers are switching from Dispensing as a sequential Process to the parallel Process of Printing. This increases the throughput of the Line by a factor of 10 to 1000.”
Objective: To establish Packaging more firmly in Europe
Christan Koenen GmbH hopes that the current funding programmes will not only benefit the frontend – i.e. Wafer Production – but also the backend, i.e. the Packaging. Michael Zahn: “In Europe, the Packaging Industry is still not very widespread. We expect some suppliers from the EMS and OEM Electronics Production sectors will establish themselves here. When that happens, there will be an increased demand for tools and know-how to establish the Printing Processes in Manufacturing. We are prepared for that.”
Packaging – Market in Motion
Dr.-Ing. Tanja Braun, group leader at Fraunhofer IZM, researches new packaging technologies for semiconductors and has received several awards for her work. In a short interview, she comments on the current trends in packaging.
Fraunhofer IZM is a leader in the development of new packaging technologies such as Panel Level Packaging (PLP). Before we talk about technology – how is the division of labour changing in the packaging market?
So far, the division of labour has been clearly defined. The “foundries”, i.e. the Wafer Manufacturers, supplied the Wafers to Packaging and Testing specialists, the OSATs. That is now changing. We see the Foundries pushing into this market, and well as entirely new players.
Source: Fraunhofer IZM
How do you explain this development?
Packaging is becoming increasingly important, and there are new technologies that allow suppliers to differentiate themselves from the competition and generate greater added value. The funding programs of the EU and Germany are certainly also contributing to a stronger focus on Packaging. The market is growing.
Your Institute has been pushing technologies such as Fan-Out Waver Level Packaging. What benefits do you see in this process?
FOWLP and FOPLP offer high integration and miniaturisation potential at low costs. Neither a Substrate or Soldering Contact is required and you do not need Bond Wires. The electrical Connection is very short, and the Contacting is purely galvanic. In addition, the Process creates the prerequisite conditions for further integration and miniaturisation, and since we use Panels instead of Wafers we can produce more Packages at the same time and save material and thus further costs.
What other Packaging trends do you see?
In the future, there will be more Chiplets. The stacking of (2.5D and 3D) structures will be increasingly applied, and we will see more PLP approaches. That is why Panel Level Packaging is one of our principal areas of research. In the first PLP Project, which started in 2016, we initially worked on basic processes together with 17 international partners. Now, in the PLP 2.0 Project, we are working on the optimisation of individual steps of Panel Level Packaging – with tremendous success.
