The fourth dimension of ATE

Phil Smith, strategic marketing manager, Teradyne Inc., Boston

In year 2000, non-memory semiconductor sales increased about one-third over 1999; and ATE for that segment zoomed up 74%. We managed to track the upswing by using temporary labor to meet production staff needs, and subcontracting took off in Asia, creating wafer fab and test houses that rival the very best operations in traditional integrated device manufacturers. But, as we all know, things changed in 2001 significantly, with non-memory IC revenue falling 30% and ATE sales plummeting by two-thirds.

Through this latest cycle, production ATE strategy remained pretty much the same. During the upturn, the important question was simply, „How can I get the test capacity to meet my shipment volumes?“ Most companies, worrying about losing ground to competitors, simply bought more of what they already had. Change during the steep production ramp was too risky. As production boomed and the machines kept coming, some managers wondered if there was another way.

One alternative to full functional test is DFT. Design-for-test has long been used for digital devices to improve fault coverage and manage complexity. With increased chip volumes, DFT advocates found new potential converts to the goals of shorter development times, less expensive testers and higher fault coverage. DFT was already being used for memory, microprocessor, and also for the largest SOC (system-on-chip). But consumer chips use real world interface IP (intellectual property) cells where DFT techniques are still immature. SOC makers responded by adding full functional testing for those ports. The very definition of a DFT tester has now changed to include functional test – on some IP cells, in some insertions, on the same tester. So, what other alternatives are available? How can an IC maker select ATE to help be competitive during the next upturn?

Conventional ATE evaluation criteria use three dimensions: device coverage, cost and time-to-market. Device coverage usually comes first – can you test the part? Cost (whether cost-to-test measured per good device shipped or tester price) is increasingly important as chip prices fall while complexity rises. Some said that ATE was not scaling with Moore’s law, echoing a concern that there are not enough engineers or hours in the day to get the work done. ATE buyers who selected individual platforms along conventional metrics began to wonder if there was another alternative.

Some ATE makers offered a „single system strategy“ as the answer: purchase one big system and stuff it with everything you need to get the job done. A single system would hold all the instrumentation for a wide range of devices (a potential utilization advantage), and would shorten development time by reducing waste from managing multiple software platforms. The single-system approach does have advantages, but test systems that are focused can be more optimized. A machine focused on consumer IC test costs less than the single system, and ATE targeted at communication chip testing has higher throughput due to architectural advantages. Systems offering performance for leading-edge users have a technical edge over single-system approaches that favor lower cost. So, while a single-system technique offers a convenience advantage, it has other costs. How should ATE buyers choose? The answer lies in a different direction.

There is a fourth dimension of a test system: flexibility. Evaluating ATE for device coverage, cost to test and time-to-market is not enough. We also need to measure the ability of a system to change. Besides asking about device coverage, we need to ask, „How easily can I change the instrument mix?“ We need ATE configurations that can change on the production floor, not just at the time of purchase. While we measure ATE capital cost and cost to test, we need to ask, „What cost and throughput choices can I make?“ We need ATE that shifts from low-capital cost, single-site testing to quad or octal site for SOC, to 32 sites or more for smart card chips. The ATE architecture needs to address the DSP (digital signal processor) needs of communi-cation and analog testing, since those cells are virtually everywhere. And while in the past we rated software for ease-of-use and completion, we now need to ask, „How does your software let me move freely from new user to test expert?“

Dynamic ATE is beginning to appear, with systems designed for flexibility from the ground up. These systems are characterized by their production capacity range, not the number of special purpose digital or analog slots ordered at the time of purchase. On dynamic ATE, configuration is in the hands of the owner and changeable as device shipment needs vary – once a week, once a day, or even more often through software performance enabling. The ATE instruments are essentially self-contained testers, performing multiple test functions at any clock rate the device requires; changing setups on-the-fly for fast test time. This class of ATE has a development environment that new users recognize immediately, but that allows experts to dig in and control every aspect of test.

We’ve managed to survive last year’s downturn, with indicators showing promise for the coming year. Consumer confidence is up, IC production is coming back. Technology continues to advance with 3G (UMTS) cellular, wireless LAN, and Gigabit data buses, continuing the shift to make everything digital and fit in our pocket. How do we get ready for the next peak? By applying the same management solution to test that we successfully used for meeting production labor needs before – plan for change. Gone are the days of static, hard tooled ATE. We have to plan our next system evaluation around another dimension of test: flexibility.

Teradyne’s Integra Flex presents the next step in IC production test. Changing the rules about what defines a tester, a universal slot tester-in-a-testhead architecture brings configuration freedom, breaking down walls that previously separated digital, analog, microwave and SoC (system-on-silicon) testers. Users can dynamically match system configuration to changing production needs to more easily manage in the high-mix, high-volume consumer IC market. Initially it targets digital, power, and baseband ICs with expansion into microwave and VHF coming soon.

Not only is all the digital totally in the head but the analog as well. The instruments go into a universal slot backplane, any board fits in any slot. This barrier-free environment lets IC makers select exactly the configuration they need for today’s production requirements while knowing that they can easily change instrument set as their device mix changes. Integra Flex gets its lower capital cost and higher throughput by combining Integra J750 high-density CMOS digital with Catalyst mixed-signal architecture. Digital speed is doubled to over 200MHz with all pins single-ended or differential. IG-XL software sees a major upgrade, adding mixed-signal, real-time control and a background DSP architecture.

All instruments are self-contained, featuring clock, data, dynamic setup memories, and secondary functions like DC parametrics and time measurement built-in. High-density designs allow to deliver over 1000 digital pins or hundreds of analog pins at the DUT board. But Integra Flex is not just about a wide instrument set, economic and time-to-market goals drive the new tester as well. Time Tracks, multiple independent clock and sequencers per DUT socket, help define another level of efficiency. When combined with multi-function SoC tester-per-pin instruments, TimeTracks allow multi-site concurrent test. More sites and more IP cores tested at once mean a step function test economics improvement.

Background DSP gets a site count boost. The idea is simple: move and process captured device data in parallel (in the background), while testing continues. Data movement and DSP calculations can add 20 to 50% more test time on conventional test systems without this background feature. Integra Flex raises background performance even higher. Internal data bandwidth doubles and processing power jumps an order of magnitude, driving test times down and site count up for analog and SoC applications.

The multi-level IG-XL5 helps beginners come up to speed with object-oriented graphic programming while providing procedure and code-based access for power users. Programming levels can be intermixed within a test program. IG-XL5 also goes from single-site to multi-site instantly, moving parallel production economics earlier in the device life cycle. Teradyne also provides Integra Flex with closed-loop, design-to-production tools: pre-silicon debug, interfaces to third-party BIST (build-in-self-test) structures, DFT failure diagnosis, and yield monitoring for faster time-to-volume. „High volume, high mix manufacturing is changing the nature of test,“ said Jeff Schneider, semiconductor test marketing manager. „We need peak economics for volume runs combined with fast reconfiguration to match device mix shifts. Integra Flex offers both.“

Integra FLEX will be demonstrated April 16 to18 at Semicon Europa in Munich, Germany.

Waren bisher ausschließlich bei der Evaluierung von Halbleiter-Testsystemen die Fragen relevant, welche Bausteine lassen sich damit prüfen, wie hoch sind die Testkosten und wie schnell läßt sich damit nach den ersten Silizium-Mustern der Markt per Serienfertigung bedienen (time-to-market), so kommt nun als weitere herausragende Frage jene nach der Flexibilität des Equipments zum tragen. Dabei geht es darum zu klären, wie rasch kann ein Tester als Folge geänderter Bedingungen umkonfiguriert werden und so gezielt dem Bedarf angepaßt werden?

Alors que jusqu’à présent, les questions importantes quant à l’évaluation des systèmes de test pour semi-conducteurs étaient de savoir quels composants il était possible de tester, quels étaient les coûts des tests et en combien de temps il était possible d’approvisionner le marché en série après les premiers échantillons (time-to-market), la flexibilité de l’équipement de test est aujourd’hui un critère majeur. Il s’agit en l’occurrence de savoir en combien de temps un testeur peut être reconfiguré suite à une modification des conditions et être ainsi adapté aux besoins.

Nei procedimenti d’evacuazione di sistemi di test per semiconduttori finora ci si poneva più che altro la rilevante domanda di quali componenti modulari potevano essere più adatti ai test, dell’entità dei costi e con quale rapidità poter impiegare il primo campione di silicio presente sul mercato in produzione di serie (time-to-market), mentre adesso ci si deve confrontare con un’ulteriore sfida, cioè, la questione della flessibilità offerta nell’equipaggiamento. Qui si tratta di chiarire con quale rapidità si può modificare la configurazione di un tester in seguito ad un cambiamento delle condizioni ed adattarlo successivamente in modo mirato alle esigenze?