Teradyne and Synopsys have formed a partnership targeted at DFT (design-for-testability) solutions, to achieve lower cost, higher yield and faster time-to-market for their customers in the semiconductor arena. The co-operation will include creating software links between automated test equipment (ATE) and DFT-related electronic design automation (EDA) tools, making higher efficiency in system-on-chip (SoC) design and production possible. The two companies will focus first on developing direct interoperability between the TetraMAX automated test pattern generation (ATPG), with built-in failure diagnosis capability, and ATE, including the Catalyst, Tiger, J973, and J750 testers. Fast, accurate failure diagnosis is increasingly important because quicker time-to-market and higher yield are gated by how quickly and effectively defect locations in SoCs are identified and remedied. The high level of integration in SoC devices in particular accentuates the need for fast defect localization methods. Given the increasing use of DFT tests like scan, the best method to identify defect locations is leveraging diagnostic capability. However, SoC manufacturers face considerable difficulty in executing DFT-based failure diagnosis due to the lack of standardized links and tools between design and ATE. DFT-based diagnosis is underutilized, limiting the potential for faster production ramp-up and higher yield
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