Homepage » Allgemein »

Promising momentum from paste printing

ProFlow provides very flexible and cost-efficient way of in-line wafer bumping
Promising momentum from paste printing

Advanced technologies such as chip-scale package (CSP) and systems-in-package or in-a-chip (SiP or SoC) offer the electrical performance and small outline required to enable the next generations of com-prehensive electronic products. Backend processing and equipment with this technology based on flipped chips, have to be more flexible, and better suited to in-line deployment to produce the packages cost-efficiently.

Neil MacRaild, DEK Printing Machines

Packaging and interconnection have a crucial impact on how fully the power of deep-submicron silicon can be accessed and exploited. Not only must packaging offer adequate electrical performance, it must also deliver it at low expense if the cost advantages of deep-submicron fabrication are to be maximized.
There is much interest in chip-scale packaging, defined as an encapsulation typically no more than 20% larger than the tiny semiconductor die itself. One of the most advanced inventions in terms of technology and space/volume requirements is the wafer-level CSP (WL-CSP). Here, solder bumps are deposited directly onto ohmic contacts on the silicon wafer before this device is reflowed to create a firm mechanical and electrical interface by combined die and substrate, ready for placement of the component in an advanced surface-mount assembly environment. This technology eliminates the gold bond wires that traditionally make the connection between a die and the separate lead frame.
The solder bumps may be deposited on the wafer surface as pre-formed solder balls or as bricks of solder paste. There are several ways to achieve this, and one of the challenges facing developers of WL-CSP and other flipped-chip methods is to deliver the package advantages in a process that is compatible with high-volume manufacturing, and is cost efficient.
Basics of wafer bumping
Wafer bumping can be achieved using sputtering or electroplating processes, but these require very specialized, high-value equipment, whereby electroplating is a highly critical wet-chemical process that requires variable current control throughout the procedure to achieve an optimum deposit profile. It also requires photoresist imaging and cleaning stages as part of the process, which add complexity, introduce a number of control issues and are difficult to build into an in-line production facility, requiring significant operator intervention before bumped wafers can be delivered to backend processing successfully.
Alternatively, mass imaging of material is capable of depositing solder bumps with sufficient accuracy, and offer the opportunity to create an automated process flow more easily, using equipment that leverages technologies already in service with most SMT-board assemblers. In wafer-level applications, the technique offers potential savings in capital investment and process footprint, and is also easily changed from ball placement to solder-paste imaging quickly and at low cost. This flexibility allows semiconductor manufacturers as well as contractor specialists to change over quickly to produce a range of different CSP styles. Importantly, the cost structure and flexibility of mass imaging also allows manufacturing services businesses to integrate wafer-level processing into existing in-line SMT assembly capabilities.
DEK has developed an award-winning equipment and process for in-line wafer-level and substrate-level processing. As this equipment is entering service with component manufacturers and packaging specialists, it is possible to assess the value of mass imaging to customers seeking a feasible manufacturing solution to the demand for advanced packages.
Solder-ball placement
A suitable solution to solder-ball placement is required at the wafer level and at the substrate level to enable a viable flip chip process. When reflowed, solder balls at the wafer level are responsible for attaching the upside down die to the substrate. First, flux is deposited at each interconnect location. Using DEK’s expertise in highly accurate paste printing for 6-sigma processes in SMT manufacturing, an exceptionally controlled, very accurate flux-deposition process is possible. Then, using enclosed head imaging based on DEK’s ProFlow imaging process, solder balls at diameters from 12mil (0.3mm) to 30mil (0.75mm) can be placed directly in precise locations on the wafer as defined by the stencil apertures.
The ProFlow derived head provides the means to control the delivery of solder balls to the stencil surface. The relative lack of friction compared with a gravity-feed process means solder balls arrive in perfect condition, not damaged or misshapen. Moreover, the DirEKt Ball Placement transfer head ensures that each node in the grid array is populated with a single solder ball; nothing is left to chance, as with the gravity process. The solder ball is also seated firmly in the flux deposited during the first stage process, under a controlled deposition force exerted continuously by the transfer head. This process can successfully place solder balls at the wafer level. The entire procedure, including the pair of imaging machines, can be purchased at lower cost than a dedicated ball-placement machine. It occupies a smaller footprint on the shop floor and achieves higher first-pass yield without rework. According to specialist packaging contractors, who are very familiar with the economic realities of the issues, the charge for rework is a significant factor influencing the total cost of ownership.
DirEKt Ball Placement is able to offer an extremely viable way to place solder balls, for creation of WL-CSP packages. And the solution has another important advantage: it is extremely easy and cost effective to change over from solder-ball placement to solder-paste deposition as a means of bumping the wafer.
Two distinct processes – one flexible platform
The ability to change over from ball placement to paste deposition allows a contract wafer-bumping business, for example, to offer greater capabilities to its customers, and to achieve a much faster return on its investment in capital equipment. Moreover, as the technology surrounding wafer level and other advanced-packaging styles continues to change rapidly, this flexibility is extremely valuable.
To achieve the target reflowed bump height in each case requires rigorous application of design rules when creating the stencil. It is also necessary to pay careful attention to the design of bond pads, allowing sufficient contact area to achieve enough solder-joint strength for a given stand-off. These are some of the issues DEK process specialists have solved in order to refine the process for production applications. The result is a highly automated process featuring a wafer-handling system that allows in-line bumping with very low operator intervention. The wafer handler was developed by DEK in conjunction with Adept Semiconductor Equipment Division of Livermore/California, and is a crucial element of the overall wafer bumping solution. This process is currently in operation at chip-scale packaging businesses.
DEK has also developed dedicated ProFlow heads ideally suited to ultra-fine pitch bumping using low alpha solder pastes. As these are specialized, expensive compounds, the ability of the ProFlow technology to control handling and minimize deterioration and wastage delivers a valuable cost saving.
Substrate bumping
Placing solder balls on FR4 epoxy substrate is a further essential process for advanced packages such as flip chip and system-in-a- package (SiP) which has arrived as an alternative to system-on-a-chip (SoC) fabrication of custom ICs. It has emerged to support greater flexibility for system designers, who can implement a number of functional blocks on separate dies. This allows systems to be fabricated on a mixture of different processes, for example combining standard CMOS with a more exotic technology such as gallium arsenide (GaAs) or silicon germanium (SiGe) to maximize RF performance. Using SiP, multiple dies can be packaged together on a single substrate to achieve high integration and low overall component count, with low interconnect density, very similar to the familiar multi-chip module concept. SiP may employ wafer-level bumping to attach bare die to the substrate, with substrate-level bumping providing interconnect to the board assembly.
The DirEKt Ball Placement process is equally applicable at the substrate level, and has been developed to allow processing of substrates in pallets, boats, strips or panels. Again, first-pass yield is very high, with the solder balls being handled significantly better than in traditional gravity-feed equipment. The preliminary fluxing stage is extremely accurate, and the process is highly automated.
Alpine Microsystems has recently entered volume production of SiP devices, using mass imaging for wafer level and substrate level bumping. The initial requirement was to achieve a higher level of automation than its existing process. Using handling systems for wafers and substrates, combined with variants of the patented ProFlow head developed specifically to satisfy the requirements of solder bumping, the company has now implemented a flexible, in-line wafer and substrate-bumping facility. In practice, Alpine has also found that changeover and tooling costs are significantly lower than traditional, dedicated bumping systems.
ZUSAMMENFASSUNG
Für die Montage von geflippten Chips/Dies auf dem Trägersubstrat vewendet man bei Advanced-Packages zur Kontaktgabe Lotkügelchen (Solder Balls, Solder Spheres). Je höher der Pincount der Packages nun wird, um so deutlicher treten die Vorteile des Schablonendrucks von Lotpaste auf die noch ungeteilten Wafer mit anschließendem Aufschmelzen zu Lotkugeln in Erscheinung. Diese Technik kommt aus der SMT-Baugrupenfertigung, wo es sich um einen seit über 20 Jahren bewährten Standard handelt.
RÉSUMÉ
Pour le montage des flip chips/dies sur le substrat, on utilise dans le cas des advanced-packages des petites boules de soudure (solder balls, solder spheres) pour établir le contact. Plus le nombre de broches des packages est élevé, plus les avantages de l’application de la pâte par sérigraphie sur les pads encore non séparés, suivie de la fusion en boules, sont évidents. Cette technique provient de la fabrication de cartes SMT où elle s’est établie comme un standard éprouvé depuis plus de 20 ans.
SOMMARIO
Per il montaggio di Chips/Dies lavorati a flipp sul substrato portante si impiegano le palline di saldatura impiegate negli Advanced-Packages per la trasmissione del contatto (Solder Balls, Solder Spheres). Quanto più aumenta il Pincount dei Packages, con tanta più sensibilità si manifesteranno i vantaggi della stampa a modello con la pasta di saldatura sui Waferpads ancora intatti, cioè non divisi, con la successiva fusione delle palline di saldatura. Questa tecnica ha origine dalla produzione di gruppi modulari SMT, dove si tratta di uno standard affermatosi da oltre 20 anni.
Current Issue
Titelbild EPP EUROPE Electronics Production and Test 11
Issue
11.2023
READ
Newsletter

Subscribe to our newsletter now

Webinars & Webcasts

First hand technical knowledge

Whitepapers

Find all current Whitepapers here

Videos

Find all current videos here


Industrie.de Infoservice
Vielen Dank für Ihre Bestellung!
Sie erhalten in Kürze eine Bestätigung per E-Mail.
Von Ihnen ausgesucht:
Weitere Informationen gewünscht?
Einfach neue Dokumente auswählen
und zuletzt Adresse eingeben.
Wie funktioniert der Industrie.de Infoservice?
Zur Hilfeseite »
Ihre Adresse:














Die Konradin Verlag Robert Kohlhammer GmbH erhebt, verarbeitet und nutzt die Daten, die der Nutzer bei der Registrierung zum Industrie.de Infoservice freiwillig zur Verfügung stellt, zum Zwecke der Erfüllung dieses Nutzungsverhältnisses. Der Nutzer erhält damit Zugang zu den Dokumenten des Industrie.de Infoservice.
AGB
datenschutz-online@konradin.de