Specialist firm Goepel has developed the next generation of CION (configurable I/O network), parallel I/O ICs with boundary-scan architecture. The CMOS chip supports a variety of signal classes up to mixed-level applications due to its wide operating voltage range. ”The increase of components supporting boundary scan is the basis for advancement of this technology“, underlines managing director Thomas Wenzel. „The CION transceiver architecture provides a highly flexible solution for design-for-testability.„ It has been optimized for low and ultra-low voltage applications, so the four 8bit ports are independently programmable each from 1.8 to 5V. The different operating modes allow the IC to be used as a pure 32bit BS transceiver or as a special 8/16bit bus transceiver. Features such as the increased output current and hot-swap ability permit application as I/O circuit. The efficient architecture allows each signal pin to be independently set as input, output or tri-state. The output cells’ unstress feature is important for production test. This capability protects both the device as well as connected circuitry against defects due to possible excessive current. In addition to the standard, the chip supports optional instructions including Idcode, Highz, Clamp and Shortex. The latter, for example, in conjunction with a TCK frequency of 30MHz provides for effective in-system programming of Flash devices. A BSDL (boundary scan description language) file is available.
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