IMEC launched its advanced packaging and interconnect center (APIC) in Leuven, Belgium, which is committed to play a central role in bringing together the different players in the IC food chain around joint research programs for integration technologies. Focus lies on bridging the ‘interconnect gap’ between circuit and system, heterogeneous integration of RF-components and thermal management in high-power density devices. The center gathers a number of competences to tackle the challenges for packaging and system integration. APIC offers solutions that are vertically and horizontally organized. Vertically in terms of technologies that range from the circuit up to the system level, and horizontally, because each level is supported by experienced teams in design, processing, analysis and reliability. This broad range feeds a number of R&D programs with an IC-centric approach, and the projects driven by the semiconductor technology roadmap and by miniaturization. The activities aim at prototyping, characterization and reliability testing. Manufacturability and low-cost processing are key elements along the way. APIC groups more than 30 partners including integrated device manufacturers (IDMs), system houses, packaging, assembly and test houses, equipment and material suppliers and fabless companies.
It starts with two programs 3D-stacked IC (3D-SIC) and 3D systems-on-chip (3D-SoC). The 3D-stacked ICs – characterized by short high-density interconnects between the chips, showed advantages concerning power and performance, and the ability to interconnect chips with divergent process flows. The Si-through connections are realized during the foundry process, between the frontend and backend of line. The 3D-SoC program points to heterogeneous integration of systems in which circuit blocks (tiles) on a die are interconnected to blocks on another die after passivation, without passing through the regular chip I/O pads. Each of these dies may be manufactured using a different technology, realizing 3D-connections after the Si-foundry process (post-passivation), using wafer-level-packaging (WLP) technologies. The target dimensions of the through-Si connections are diameters down to approximately 25µm and pitches down to 50µm, for wafers thinned down to 200 to 50µm. The completion of low-resistance, low-capacitance and low-cost through-wafer interconnects is a major target for the 3D-SoC technology design. Special attention is given to through-Si via reliability and RF-through applications.
EPP EPE 410
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